1. Field of the Invention
The invention relates to the field of metal-oxide-semiconductor dynamic random-access memories (RAMs).
2. Prior Art
Dynamic random-access memories (RAMs) fabricated with metal-oxide-semiconductor (MOS) technology are well-known. Most often the cells of these memories consist of a single active device (a field-effect transistor) and a capacitor for storing charge. Examples of such memories are described in U.S. Pat. Nos. 3,858,185; 4,038,646; and 4,247,917.
In many MOS RAMs, a single location in memory is accessed for each address applied to memory. That is, the memory "chip" is organized, for instance, as a 64K.times.1 memory. More recently, MOS RAMs are fabricated where 8 locations in memory are accessed for each address to provide special compatibility with 8-bit buses. These memories present unique design problems in that more lines are required on the chip to carry the input and output data. Often these lines are metal lines, requiring considerable area. Consequently, unique designs are required if substrate area is to be held to a minimum.
Applicant has filed another application covering a byte wide dynamic RAM entitled "BYTE WIDE DYNAMIC RAM", Ser. No. 192,740, filed Oct. 1, 1980 and assigned to the assignee of the present application.